This paper describes Silicon Labs’ new Precision32™ microcontrollers, the company’s first 32-bit
MCUs. In addition to the ARM-compatible CPU, the chips integrate USB and a set of analog
components along with the usual flash memory, SRAM, timers, and serial interfaces. This paper
is sponsored by Silicon Labs, but all opinions and analysis are those of the author.

This white paper examines QLogic's third-generation converged network adapter (CNA) technology, which combines elements from the company's Fibre Channel HBA, iSCSI HBA, and intelligent NIC product lines. This paper is sponsored by QLogic, but all opinions and analysis are those of The Linley Group.

This white paper examines the need for Suite B security, the underlying technology, chip-level requirements, and real-world implementations. This paper is sponsored by Exar, but all opinions and analysis are those of The Linley Group.

This paper describes the lengthy effort behind Marvell's launch of their Sheeva processor line. We examine these new processors and their applicability to communications, printers, storage, consumer, and mobile applications, and provide a peek at some next-generation CPUs. This paper is sponsored by Marvell, but all opinions and analysis are those of The Linley Group.

This paper examines the trend toward combining control-plane and data-plane processing on a single chip. It discusses the technologies driving this trend, the common features of these chips, their advantages and disadvantages, and how they are being deployed today and into the future.